About the Role
Job Summary
We are looking for a skilled SoC Design Verification Engineer with strong experience in SystemVerilog and UVM . In this role, you will be responsible for verifying complex System-on-Chip (SoC) designs and ensuring functional correctness, performance, and reliability.
Key Responsibilities:
- SoC/IP/Subsystem verification using SV-UVM .
- Develop verification plans, test benches, and test cases.
- Verify high-speed protocols: PCIe, Ethernet, CXL, MIPI, DDR, HBM .
- Perform gate-level simulations and power-aware verification (UPF, Xprop).
Requirements:
- 5+ years of SoC/IP/Subsystem verification experience.
- Strong hands-on experience in SystemVerilog and UVM .
- Experience in complex SoC verification projects.
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