About the Role
Job Summary
We are looking for a skilled So C Design Verification Engineer with strong experience in System Verilog and UVM. In this role, you will be responsible for verifying complex System-on-Chip (So C) designs and ensuring functional correctness, performance, and reliability.
Key Responsibilities:
So C/IP/Subsystem verification using SV-UVM.
Develop verification plans, test benches, and test cases.
Verify high-speed protocols: PCIe, Ethernet, CXL, MIPI, DDR, HBM.
Perform gate-level simulations and power-aware verification (UPF, Xprop).
Requirements:
5+ years of So C/IP/Subsystem verification experience.
Strong hands-on experience in System Verilog and UVM.
Experience in complex So C verification projects.
We are looking for a skilled So C Design Verification Engineer with strong experience in System Verilog and UVM. In this role, you will be responsible for verifying complex System-on-Chip (So C) designs and ensuring functional correctness, performance, and reliability.
Key Responsibilities:
So C/IP/Subsystem verification using SV-UVM.
Develop verification plans, test benches, and test cases.
Verify high-speed protocols: PCIe, Ethernet, CXL, MIPI, DDR, HBM.
Perform gate-level simulations and power-aware verification (UPF, Xprop).
Requirements:
5+ years of So C/IP/Subsystem verification experience.
Strong hands-on experience in System Verilog and UVM.
Experience in complex So C verification projects.
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