Full-time

Verification engineer for VLSI departmen

Posted by Confidential • גוש דן, גוש דן, Israel

📍 גוש דן, גוש דן 🕒 March 01, 2026

About the Role

תחום:


A leading company is looking for a verification engineer for vlsi departmen



דרישות:

BSc in HW engineering or Electronics engineering
0-5 years of experience in Advanced ASIC RTL Design (not verification component)
Knowledge in: Verilog & simulation, perl & TCL scripts, Linux
Experience in processor design or memory subsystem design
Experience in low power technics in RTL level


איזור: גוש דן


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