Full-time
SysVerilog UVM Verification Engineer (FPGA/ASIC) Mandarin
Posted by Oppstar Berhad • Bayan Lepas, Penang, Malaysia
About the Role
A technology company in Penang is seeking a verification engineer with expertise in FPGA/ASIC design. The role involves performing pre-Si verification, defining test plans, and developing test benches using System Verilog/UVM. The candidate must have a BSEE/MSEE/PhD with at least 3 years of relevant experience. Mandarin-speaking is essential. The position is onsite, and experienced candidates may also be considered for a KL location.
#J-18808-Ljbffr
#J-18808-Ljbffr
Ready to Apply?
Submit your application today and take the next step in your career journey with Oppstar Berhad.
Apply Now