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Staff Engineer, Physical Design

Posted by Renesas Electronics • Hyderabad, Telangana, India

📍 Hyderabad, Telangana 🕒 March 02, 2026
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About the Role


Job Description

We are looking for a Staff/Senior Staff Engineer with deep expertise in Logic Synthesis and/Or Static Timing Analysis (STA). This role involves driving RTL-to-gate-level implementation, timing closure, and optimization for complex SoCs across advanced technology nodes.

Key Responsibilities

  • Perform logic synthesis for large-scale ASIC designs using Synopsys Design Compiler and Cadence Genus.
  • Develop and optimize multi-mode, multi-corner (MMMC) constraints for synthesis and STA.
  • Conduct Static Timing Analysis using PrimeTime/Tempus for sign-off across multiple corners and modes.
  • Implement timing closure strategies, including ECOs, buffer insertion, and cell sizing.
  • Collaborate with RTL, Physical Design, and DFT teams to ensure design quality and schedule adherence.
  • Automate flows using Tcl, Perl, Python scripting to improve efficiency.
  • Mentor junior engineers and lead timing closure efforts.

    • Job Details

    • Location Hyderabad, Telangana
    • Job Type Full-time
    • Category Engineers
    • Posted March 02, 2026
    • Deadline April 11, 2026

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