Sr Staff Digital Verification Engineer

-Understanding the expected functionality of designs.

-Designing and developing verification environment

-Improve the verification architecture and flow

-Running RTL and gate-level simulations/regression.

-Code/functional coverage development, analysis and closure.

-MS in CS/ME.

-Minimum of 8 years’ experience.

-Candidate should be familiar with as System Verilog, UVM verification.

-Candidate should be familiar with industry standard ASIC design and verification tools and flow.

-Candidate should be familiar with basic computer architecture

-Additional qualifications include: Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.

Requirements

-Verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).

-Independent and self-managing.

-Scr...