About the Role
Job Description
Design optimized digital blocks meeting functional, cost and low power constraints and ensure spec compliance.Cover digital backend design from synthesis, upf, static timing analysis and logic equivalent checking.Interface with P&R for digital hand-off and post layout verification.Collaboration with analog engineers and test engineers on analog testability design and debugging.Work closely with Application/GUI team in FPGA prototype and lab debugging.Perform physical silicon device evaluation where necessary.
Qualifications
10+ years of experience in ASIC/IC design with deep knowledge of whole IC design flow from RTL coding, synthesis, static timing analysis, logic equivalent checking to post-layout checking.Experience in DFT or physical design is a plus.Experience in FPGA prototype and lab equipment and lab debug is a plus.Fluent in either Verilog RTL coding and ASIC d...