Full-time

Sr Principal Design Engineer

Posted by Cadence Design Systems, Inc. • Sector 8, Uttar Pradesh, India

📍 Sector 8, Uttar Pradesh 🕒 March 03, 2026

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About the Role

Description
 :RTL Design Engineer for DDR Memory Controller IP development team.
The role would include the design and support of the RTL of the DDR Memory Controller solution of Cadence. All leading DDR memory protocols will be supported – including DDR4/LPDDR4.
The work involved will be working with the existing RTL, the addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring the design is clean for LINT and CDC design guidelines.

Position Requirements:
BE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI with experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.
RTL Design using Verilog is a must.
System Verilog experience and experience with UVM based environment usage / debugging is required.
AXI3/4 experience is d...
                

Job Details

Location Sector 8, Uttar Pradesh
Job Type Full-time
Category Engineers
Posted March 03, 2026
Deadline April 12, 2026

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