Full time

Sr. Principal Design Engineer

Posted by Cadence Design Systems, Inc. • Sector 8, Uttar Pradesh, India

📍 Sector 8, Uttar Pradesh 🕒 June 10, 2026

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About the Role

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Responsibilities :
Design Verification for interconnect IP and Tensilica Processor subsystems.
Relevant experience in interconnect and subsystems is strongly preferred
Crafting verification plans and executing on those plans to verify highly complex and configurable designs.
Responsible for coverage collection and closure
Work closely with cross functional teams (DV/Arch/Design/FW) to identify coverage scope
Responsible for creating / working with UVM based DV environment.
Required Skills and Experience:
10+ years of design verification experience
BS (or higher) in EE/Computer Engineering
Strong technical and interpersonal skills
Excellent knowledge of Interconnects, NoCs and design verification fundamentals.
Excellent knowledge and command ov...
                

Job Details

Location Sector 8, Uttar Pradesh
Job Type Full time
Category Engineers
Posted June 10, 2026
Deadline July 20, 2026

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