SoC Design Verification Lead

Overview

A Design verification Lead responsible for leading SoC architecture verification, creating verification strategy, developing test cases and test bench using UVM methodology, and coordinating cross‑functional efforts to achieve full coverage verification plans.

Responsibilities

• Lead pre‑silicon verification strategy and execution for SoC verification
• Perform functional logic verification at multiple levels (block, subsystem, and full chip)
• Define and develop scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet required coverage and acknowledge microarchitecture specifications
• Document, review, and execute verification strategy plan on different methodologies/techniques (e.g., gate‑level simulation, power‑aware simulations) to enable feature coverage as per the microarchitecture specifications
• Execute verification plans and...