Responsibilities
Testbench and test sequence development for verification of new controller technologies and featuresFunctional coverage planning, coverage item coding, and test suite augmentation to achieve Functional CoverageRegression test development, monitoring, debug/triage, and correction to test environment, sequences, debug of controller RTL designDevelopment & support of Verification environment scripting and capabilitiesQualifications
Bachelors Degree or above in EE/CS, at least 4-6 years experience with HDL logic Design-VerificationSystem Verilog / UVM testbench, Verilog/System Verilog logic design/RTL fluency a mustPre-existing Experience / familiarity with PCI-Express controller and protocol requiredWorking experience with Python and TCL scripting languages preferredRambus is a global company that makes industry-leading mem...