Senior/Staff DFT Engineer

Senior DFT Engineer – Multicore In-Memory-Compute SoC Team

Position Overview

Design, implement, and validate test solutions for our complex SoCs in a fast‑moving startup environment.

Seniority level: Mid‑Senior level. Employment type: Full‑time.

Key Responsibilities

• Implement scan insertion, ATPG, Memory BIST, JTAG/IJTAG, and fault‑simulation flows.
• Collaborate with RTL, verification, and physical design teams to integrate DFT solutions efficiently.
• Support silicon bring‑up and debug, optimizing test coverage and yield.
• Contribute to methodology improvements and share best practices.

Qualifications

• Minimum of 5 years in DFT engineering, preferably with complex SoC projects.
• Proficiency in SystemVerilog RTL, TCL, Python, Unix/Linux workflows.
• Core knowledge of hierarchical scan, ATPG, Memory BIST, JTAG/IJTAG, fault simulation, silicon debug, g...