Full-time
Senior Verification Engineer - SystemVerilog/UVM, SerDes
Posted by Confidential • toronto, on, Canada
About the Role
A leading company in digital technology is seeking a Senior Design Verification Engineer to enhance high-performance data communication systems. The role involves reviewing design specifications, leading verification tasks, and collaborating with cross-functional teams. Candidates should have strong skills in SystemVerilog and UVM, with a focus on advanced semiconductor projects in a supportive work culture.
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