Full-time
Senior Validation Engineer - Formality & LEC
Posted by Synopsys • santiago, santiago, Chile
About the Role
Synopsys in Santiago, Chile is looking for a dedicated Test and Validation Engineer to ensure the quality and reliability of their Formality product. Responsibilities include testing, root cause analysis, and reporting, working closely with R&D and engineering teams.
The ideal candidate possesses a BSc or MSc in VLSI with at least 2 years of experience. Proficiency in scripting languages like Perl, Tcl, and Python is essential for this dynamic role.
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