About the Role
A leading semiconductor company in Penang, Malaysia, is seeking a Mid-Senior level engineer for timing closure and signoff of FPGA/SoC systems. Candidates should have at least 7 years of experience, proficiency in industry-standard tools like Primetime/PTPX, and strong communication skills. This full-time role focuses on static timing analysis and collaboration with design teams. Join a dynamic environment and advance your career in semiconductor manufacturing.
#J-18808-Ljbffr
#J-18808-Ljbffr
Ready to Apply?
Submit your application today and take the next step in your career journey with Altera.
Apply Now