Senior RTL Design Engineer

Stealth Mode Start-Up - ASIC Design, RTL, Architect

We are seeking a Senior Design Engineer to lead architecture, design, integration, and implementation of advanced SoCs, with focus on high-speed interconnects, IP integration, and ASIC execution. Role emphasizes SoC integrationwith UCIe die-to-die interfaces, HBM subsystems, and custom compute cores.

Responsibilities include RTL design, IP configuration and integration, synthesis, and collaboration with physical design teams for timing closure.

Supports next-generation compute architectures, ensuring efficient interaction between UCIe, NoC interconnects, memory systems, and custom processing elements. Involves architecture definition and implementation of complex SoC and base die products.

Key Responsibilities

• Define SoC and subsystem architecture (UCIe, NoC, memory controllers, PHYs, compute cores)
• Integrate high-speed IP...