Senior Lead Engineer

Design for Test (DFT) Opportunities We are looking for passionate and driven Design for Test (DFT) professionals to join our growing team and contribute to cutting-edge silicon development. Whether you are: A hands-on technical expert who thrives on solving complex implementation challenges, or A senior leader/architect with deep industry experience shaping DFT strategies across advanced nodes, we have exciting opportunities that will challenge your skills and accelerate your career . Core Responsibilities You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery. Key focus areas include: Scan Architecture & Implementation: Implementation of Scan insertion at both RTL and Gate levels, including EDT/OCC. Block level ATPG & Coverage: Execution of Block-level ATPG, comprehensive DRC analysis, and coverage optimization. Verification: Handling Pattern simulations (both Timing and Non-timing). SOC Integration: Pattern Retargeting to SOC/Subsystem levels and per...