About the Role
Senior DFT Engineer
Location: Bengaluru, India
Experience: 3–12 Years
Role Type: Full-time | Silicon Engineering
About the Role
We are seeking a Lead Design-for-Test (DFT) Engineer to drive RTL-centric DFT architecture and execution for complex So Cs and subsystems used in high-performance compute, AI acceleration, and advanced connectivity platforms.
You will own the complete DFT lifecycle — from RTL insertion strategy through pattern generation, simulation, and silicon-quality coverage closure — while partnering with design, physical implementation, and post-silicon teams to ensure first-pass success.
This role is ideal for engineers who combine deep hands-on DFT implementation with system-level thinking and execution excellence.
What You’ll Do
Lead RTL-level DFT architecture and implementation across full So C and block/partition hierarchies
Own DFT flows using Mentor Tessent across:
Scan insertion
MBIST
OCC (on-chip clocking)
EDT compressio...
Location: Bengaluru, India
Experience: 3–12 Years
Role Type: Full-time | Silicon Engineering
About the Role
We are seeking a Lead Design-for-Test (DFT) Engineer to drive RTL-centric DFT architecture and execution for complex So Cs and subsystems used in high-performance compute, AI acceleration, and advanced connectivity platforms.
You will own the complete DFT lifecycle — from RTL insertion strategy through pattern generation, simulation, and silicon-quality coverage closure — while partnering with design, physical implementation, and post-silicon teams to ensure first-pass success.
This role is ideal for engineers who combine deep hands-on DFT implementation with system-level thinking and execution excellence.
What You’ll Do
Lead RTL-level DFT architecture and implementation across full So C and block/partition hierarchies
Own DFT flows using Mentor Tessent across:
Scan insertion
MBIST
OCC (on-chip clocking)
EDT compressio...
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