Senior Lead

Physical Design /
Location: Bangalore/Coimbatore
Typical Qualification
B.E/B.Tech/M.Tech in ECE/EEE
Strong timing fundamentals
4+years' experience
PD – Physical Design (Job Description)
Role Overview
Physical Design (PD) engineers convert RTL/netlist into a manufacturable chip layout.
Key Responsibilities
Floorplanning
Placement & optimization
Clock Tree Synthesis (CTS)
Routing
Timing closure
Power optimization
Physical verification (DRC, LVS)
ECO implementation
Required Skills
Strong digital design fundamentals
Understanding of CMOS & semiconductor basics
Static Timing Analysis (STA) concepts
Low-power design (UPF/CPF – good to have)
Familiarity with nodes like 7nm / 14nm / 28nm
Scripting: Tcl, Perl, Python
Tools Commonly Used
Cadence Innovus
Synopsys ICC2
PrimeTime (for timing signoff)
STA – Static Timing Analysis (Job Description)
Role Overview
STA engineers ensure the chip meets timing requ...