About the Role
Minimum:
- Bachelors or Masters in Electrical/Electronics/CS Engineering or a related field in HW VLSI with minimum 5+ years of industry experience.
- Good experience with any HVL and verification methodology (UVM/OVM/VMM).
- Hands-on ASIC-SoC design verification TB development & testing experience.
- Fluency with SystemVerilog randomization constraints and coverage methodology.
- Good problem-solving skills and the passion to take on technical challenges.
- Passionate about AI and thriving in a fast-paced and dynamic startup culture.
Preferred:
- Experience with C and exposure to processor-based verification environment.
Ready to Apply?
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