About the Role
Senior DFT Engineer:
Experience : 7-10 years
Location : Hyderabad
specifically with expertise in , ATPG pattern generation, fault simulation, and coverage analysis
RTL coding (Verilog/SystemVerilog), test architecture, JTAG, MBIST/LBIST, and DFT.
Interested,please share your updated resume to [email protected]
Experience : 7-10 years
Location : Hyderabad
specifically with expertise in , ATPG pattern generation, fault simulation, and coverage analysis
RTL coding (Verilog/SystemVerilog), test architecture, JTAG, MBIST/LBIST, and DFT.
Interested,please share your updated resume to [email protected]
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