Senior design verification engineer

Job Opening: So C Design Verification Engineer (IP Verification)
Experience: 7+ Years
We are seeking a highly skilled So C Design Verification Engineer with strong expertise in IP and Sub-system level verification using System Verilog and UVM. The ideal candidate will play a key role in ensuring functional correctness and quality of complex So C designs.
Key Responsibilities & Requirements:
Hands-on experience in So C-level and IP-level verification , including VIP integration , coverage-driven verification , and debugging
Strong proficiency in System Verilog/UVM testbench architecture , including assertions, scoreboarding, and functional coverage
Experience in IP and sub-system verification , including test plan creation, execution, and review
Solid understanding of verification methodologies, regression management, and debug flows
Proficiency in scripting languages such as Python or Perl for automation and regression support
Ability to collaborate effective...