About the Role
Job Opening: SoC Design Verification Engineer (IP Verification)
Experience: 7+ Years
We are seeking a highly skilled SoC Design Verification Engineer with strong expertise in IP and Sub-system level verification using SystemVerilog and UVM. The ideal candidate will play a key role in ensuring functional correctness and quality of complex SoC designs.
Key Responsibilities & Requirements:
- Hands-on experience in SoC-level and IP-level verification, including VIP integration, coverage-driven verification, and debugging
- Strong proficiency in SystemVerilog/UVM testbench architecture, including assertions, scoreboarding, and functional coverage
- Experience in IP and sub-system verification, includ...
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