About the Role
Job description:
Position: RTL Design Engineer
Location: Bangalore
Experience Level: 4+ years
Notice Period - 0 to 90 days
Roles& Responsibilities:
- Should have experience with ASIC micro-architecture development
- Expertise and hands on experience in Verilog/RTL design for IP/Sub-System or SoC.
- Command and thorough knowledge on digital logic design concepts.
- Should be good knowledge on Lint, CDC, RDC, constraint development, synthesis.
- Must have worked on at least one large IP/Sub-System block and have in depth knowledge of IP block design/architecture.
- Must have experience in Synopsys/Cadence/Mentor simulation tools and debugging skills.
- Desirable Perl/TCL scripting and automation knowledge
- Desirable experience in RTL logic synthesis, sdc and constraint writing experience
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