About the Role
Job Title: RTL Design Engineers
Exp Level: 2-3 yrs
Loctaion: Hyderabad
Job Description:
- Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog .
- Responsibilities include ASIC/SoC IP integration , linting, synthesis, and working closely with verification teams.
- Requires strong fundamentals in digital design , timing closure, and understanding of the ASIC flow.
- You'll debug simulation failures, implement ECOs, and support gate-level simulations.
- Collaborate with cross-functional teams (SW, DV, Physical Design) to achieve tapeout goals.
- Bachelor's or Master's degree in engineering in EE/CS is essential, along with 2-3 years of relevant experience.
Share resumes to
Ready to Apply?
Submit your application today and take the next step in your career journey with ACL Digital.
Apply Now