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Full-time

Principal Engineer - Chip DFT Lead

Posted by Renesas Electronics • Hyderabad, Telangana, India

📍 Hyderabad, Telangana 🕒 February 19, 2026
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About the Role


Job Description

We are seeking a highly skilled Principal Engineer – DFT Lead to drive Design-for-Test (DFT) strategy and implementation for multi-chiplet Power efficient MCU chipsx. This role requires deep technical expertise in DFT methodologies, leadership in cross-functional collaboration, and ownership of test architecture to ensure high-quality, manufacturable designs.

  • Define and develop DFT methodologies for multi-chiplet SoCs
  • Define and implement DFT architecture for multi-chiplet SoCs, including scan, BIST, and boundary scan
  • Drive test coverage goals and optimize for cost, performance, and quality
  • Develop and integrate DFT logic into RTL and physical design flows
  • Ensure seamless interaction with synthesis, timing closure, and verification teams
  • Validate DFT features through simulation and ATPG pattern generation
  • Collaborate with product engineering for silicon bring-up and yield improvement
  • Mento...

    • Job Details

    • Location Hyderabad, Telangana
    • Job Type Full-time
    • Category Engineers
    • Posted February 19, 2026
    • Deadline March 31, 2026

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