At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The candidate will perform the physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed designs at the latest technology nodes.The responsibility of the candidate includes participating in or leading next generation physical design, methodology and flow development.The candidate will work closely with RTL design team to ensure successful tapeouts.Requirement:
BS/MS in EE/CS with 3+ years of hands-on experience in physical design and verification.Experienced with ASIC design flow, hierarchical physical design...