About the Role
Senior Physical Verification Engineer
Location: Hyderabad, India
Experience: 3–4 Years
Notice Period: Immediate to 15 Days (Mandatory)
Education: B. Tech/M. Tech in Electronics, Electrical Engineering, or VLSI.
Role Objective
As a Physical Verification (PV) Engineer, you will be responsible for ensuring the physical integrity and manufacturability of complex So Cs and high-performance digital blocks. You will work on cutting-edge process nodes (7nm, 5nm, and below), driving sign-off convergence through rigorous DRC/LVS analysis and cross-functional collaboration.
Key Responsibilities
Role: Execute and debug DRC, LVS, and ERC sign-off at the block and full-chip levels using industry-standard tools like Calibre or ICV.
Core Tasks: Identify and resolve complex layout issues, including connectivity shorts, antenna violations, and density requirements on advanced process nodes (7nm/5nm).
Collaboration: Work closely with Physical Design and Layout teams to drive...
Location: Hyderabad, India
Experience: 3–4 Years
Notice Period: Immediate to 15 Days (Mandatory)
Education: B. Tech/M. Tech in Electronics, Electrical Engineering, or VLSI.
Role Objective
As a Physical Verification (PV) Engineer, you will be responsible for ensuring the physical integrity and manufacturability of complex So Cs and high-performance digital blocks. You will work on cutting-edge process nodes (7nm, 5nm, and below), driving sign-off convergence through rigorous DRC/LVS analysis and cross-functional collaboration.
Key Responsibilities
Role: Execute and debug DRC, LVS, and ERC sign-off at the block and full-chip levels using industry-standard tools like Calibre or ICV.
Core Tasks: Identify and resolve complex layout issues, including connectivity shorts, antenna violations, and density requirements on advanced process nodes (7nm/5nm).
Collaboration: Work closely with Physical Design and Layout teams to drive...
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