Physical design(3-5)

<ul> <li>Physical Design Engineer with strong expertise in Physical Verification and Static Timing Analysis to support end to end ASIC/SoC implementation in a compact, high ownership team.</li> <li>The ideal candidate will drive the complete RTL to GDSII flow, ensure signoff-quality physical verification, and manage timing closure across multiple corners and mode.</li> </ul> <p>The Physical Verification (PV) role involves running and debugging complete signoff flows, including DRC, LVS, antenna, density/fill, and ERC checks.</p> <ul> <li>It requires hands-on experience working with foundry rule decks using tools such as Calibre, ICV, or Pegasus.</li> <li>The engineer is responsible for driving closure of all physical verification violations prior to tape-out, coordinating GDS merge activities, performing final signoff checks, and preparing the necessary reports.</li> <li>Additionally, the role...