Full-time
Physical Design Engineer
Posted by Alchip Technologies • Bayan Lepas, Pulau Pinang, Malaysia
About the Role
Job Description
- Perform gate level netlist to GDS design independently including but not limited to floor planning, place & route, close tree synthesis, timing sign off and physical verification.
- Perform design IP Implementation, IR drop analysis, DFT, STA and foundry merge.
- Work with manager to achieve assigned tape out target.
Qualifications
- Bachelor or MS Degree in EE or related.
- Must has solid knowledge on digital/analog electrical; knowledge on verilog/ synthesis/ floorplan will be a plus.
- Experience of working on top level design with chip level floor plan is a plus.
- Familiar with Cadence EDI, Synopsys ICC design flow and Mentor Calibre for physical design engineer.
- Familiar with TCL/ Perl scripting and design automation.
Ready to Apply?
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