Physical ASIC Design Implementation Engineer

Join our dynamic team as a Physical ASIC Design Implementation Engineer. Contribute to cutting-edge semiconductor projects, developing top-tier technology from netlist-in to GDSII-out for both toplevel chips and blocklevel blocks in processes from N2 to 180nm. Collaborate using the full suite of Cadence Innovus Place&Route tools to drive innovation and excellence in our designs.

About the role

As a Physical ASIC Design Implementation Engineer, you will be at the forefront of technology, leveraging full backend expertise for P&R projects. You will engage directly with customers for future projects and possess a robust grasp of the Cadence Innovus Place&Route flow. You’ll also take the reins on partitioning, split the top-level SDC file into timing budget and constraints, and lead discussions on specifications with customers.

Key Responsibilities

- Lead the Physical Design implementation team through the full chip design cycle to ensure signoff ...