Full-time

Memory Subsystem RTL & Integration Engineer

Posted by AMD • Markham, York Region, Canada

📍 Markham, York Region 🕒 March 01, 2026

About the Role

A global technology leader in York Region is seeking a Memory Subsystem Design and Integration Engineer. In this full-time role, you will design and develop RTL for high-speed memory subsystems, collaborate with multiple teams, and resolve complex integration issues. The ideal candidate has experience with Verilog/System Verilog and a strong understanding of memory subsystems. AMD offers competitive pay and comprehensive benefits, reflecting skills and experience.
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