Full-time

Lead Solutions Engineer

Posted by Cadence Design Systems, Inc. • Noida, Uttar Pradesh, India

📍 Noida, Uttar Pradesh 🕒 March 01, 2026

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About the Role

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Understand/review Design specification and develop verification strategy/Test plan/coverage plan. Development of constrained random verification environments and verification components. Writing tests/sequences/functional coverage/assertions to meet verification goals. Developing c-based test cases for SOC verification.
Required experience
Strong background on functional verification fundamentals, environment planning, test plan generation, environment development
System Verilog experience and experience with UVM based functional verification environment development is required.
Good knowledge of verilog/vhdl/C/C++/Perl/Python.
Expertise in AMBA protocols. (AXI/AHB/APB).
Good knowledge of at least one of the USB/PCIE/Ethernet/DDR/LPDDR or similar protocols
Good handle on using one or more version...
                

Job Details

Location Noida, Uttar Pradesh
Job Type Full-time
Category Computer Occupations
Posted March 01, 2026
Deadline April 10, 2026

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