Full-time
Lead Physical Design engineer
Posted by Eteros Technologies • Greater Bengaluru Area, Greater Bengaluru Area, India
About the Role
Job Description
- Experience in all phases of the IC design process from RTL->GDS2
- Physical implementation of SoC/Full-chip-level and/or high-speed CPU/GPU/DSP cores
- Experience in high-speed, low-power, mixed-signal SoC’s is a plus
- Experience in developing PNR methodology/flow to and supporting a larger PD team
- Experience on floor planning, clocking & power network architecture and design
- Experience in low-power implementation using UPF/CPF power intent flow
- Experience in I/O Ring, RDL routing, bumps and other top-level design considerations
- Experience in LVS/DRC/ERC, EMIR (static & dynamic), LEC and Reliability sign-off checks
- Experience in STA analysis, timing closure and defining chip sign-off criterion
- Thorough understanding of digital design, timing analysis, and DFT
- Good understanding of foundation IP components – Standard cells, SRAMs etc.
- ...
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