About the Role
Physical Design Lead
Locations: Bangalore
Experience: 10–16 Years (VLSI Physical Design)
About the Role
We are looking for a highly experienced Physical Design Lead to own top-level physical implementation and integration of large-scale SoC and ASIC platforms. In this role, you will drive hierarchical integration strategy from netlist to GDSII, ensuring world-class PPA (Power, Performance, Area) and signoff quality across complex, multi-block designs.
You will operate at the center of architecture, RTL, IP, DFT, packaging, and signoff teams—leading execution, shaping methodology, and delivering first-pass silicon success on advanced technology nodes.
What You’ll Do
End-to-End Physical Integration
- Own top-level hierarchical physical design from netlist through tapeout
- Define and drive
Ready to Apply?
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