Lead ASIC Physical Design Engineer – Advanced Nodes

We are partnering with a cutting‑edge semiconductor company in Zürich who are building next‑generation compute technology and are now looking for a Lead ASIC Physical Design Engineer to own and scale their backend implementation capability.

This is a senior, hands‑on leadership role where you will define the RTL-to‑GDSII strategy and build the team that executes it.

If you enjoy taking complex digital designs from synthesis all the way to clean sign‑off — and you’re confident leading the toughest implementation challenges yourself — this could be for you.

You will combine deep technical execution with methodology ownership and team leadership.

Expect to:

• Define and maintain a robust RTL-to-GDSII implementation flow
• Own synthesis, floorplanning, partitioning, P&R, CTS, routing & closure
• Drive MCMM timing closure, power optimization & ECO strategy
• Establish constraint methodology, library strategy...