About the Role
Responsibilities
- 4+ years experience in semiconductor industry
- Hands-on experience with System Verilog as High-level Verification Language and UVM implementation.
- Debugging digital simulation in both RTL and gate-level netlist, isolating issues in both module and system level.
- Clear understanding of ASIC design flow
- Solid analytical, synthesis and problem solving skills
- 4+ years experience in semiconductor industry
- Hands-on experience with System Verilog as High-level Verification Language and UVM implementation.
- Debugging digital simulation in both RTL and gate-level netlist, isolating issues in both module and system level.
- Clear understanding of ASIC design flow
- Solid analytical, synthesis and problem solving skills
Ready to Apply?
Submit your application today and take the next step in your career journey with BITSILICA.
Apply Now