Full-time

IC Package Design Engineer

Posted by UST Malaysia • , Penang, Malaysia, Penang, Malaysia

📍 , Penang, Malaysia, Penang 🕒 March 01, 2026

About the Role

As a IC Package Design Engineer, you will be responsible for executing high density package layout designs across product portfolios (Test Chips, CPUs, Chipsets, SoC designs, Test Vehicles and more)

Responsibilities

  • Routing feasibility studies
  • Signal breakout & full path routing, including Length matching (Group/ Diff Pair) for Low-Speed IOs and High-Speed IOs (e.g. DDR, PCIe, SERDES)
  • Power routing
  • Package Ballmap assignment
  • VSS Stitching (Vertical/ Horizontal)
  • Design rule checks (DRCs) and DRC cleanup (e.g. Mentor DRC and PLA eDRC)
  • Adhesion hole generation and touchup
  • Routing over void report generation and fixes
  • Return path report generation and cleanup
  • Using the Mentor Graphics Xpedition PCB software to design the substrate in compliance with existing design rules, electrical requirements, and processes
  • Work together with assigned PDE to deliver Package d...

Ready to Apply?

Submit your application today and take the next step in your career journey with UST Malaysia.

Apply Now