IC Layout Engineer

We are looking for aIC Layout Engineer with experience inGPIO and I/O cell design to join our growing team. You will be responsible for the physical layout implementation of GPIO blocks, ensuring compliance with design rules, reliability standards, and integration into top-level chip designs.

Key Responsibilities

• Performlayout design for GPIO and other I/O-related circuits based on schematics and design guidelines
• Handle floorplanning, device placement, and routing of transistors, pads, ESD structures, and guard rings
• Ensure DRC, LVS, and ERC compliance
• Implement ESD protection and follow latch-up prevention measures
• Collaborate with circuit design engineers to meet performance, timing, and reliability requirements
• Support parasitic extraction (PEX) and assist in post-layout simulation
• Contribute to top-level pad ring integration and interface with multiple power domain...