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Full-time

Hardware Design Engineer

Posted by Rambus • Hillsboro, Oregon, United States

📍 Hillsboro, Oregon 🕒 February 19, 2026
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About the Role

Responsibilities

  • Design architecting and trade-off analysis

  • RTL coding and verification

  • Memory Controller + PHY integration and verification

  • Customer delivery and support

    • Qualifications

    Strong System Verilog/Verilog RTL design expertise


  • Questa/Incisive/VCS simulator experience

  • Python/Perl/Tcl scripting experience

  • Significant ASIC and/or FPGA design experience

  • Ability to learn quickly and work independently

  • Solid communication and project management skills

  • 5+ years of logic design experience

  • BSEE

    • Definite Plus:


  • ASIC synthesis, timing constraint, CDC/RDC experience

  • Verification experience

  • Memory (HBM, GDDR, LPDDR, DDR) expertise

  • AMBA AXI or CHI design experience

  • Located in the Hillsboro, Oregon area

    • Training:

  • Provided as needed

    • Job Details

    • Location Hillsboro, Oregon
    • Job Type Full-time
    • Category Engineers
    • Posted February 19, 2026
    • Deadline March 31, 2026

    Ready to Apply?

    Submit your application today and take the next step in your career journey with Rambus.

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