Formal Verification Engineer

Minimum Qualification:

• Bachelor's/ Master's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 3-10 years of experience with formal verification ASIC design.
• Experience writing formal properties using System Verilog Assertions (SVA).
• Experience with EDA tools (e.g., JasperGold, Questa Formal, VC Formal

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering or Computer Science.
• Experience with scripting languages.
• Knowledge of specific formal applications, abstraction techniques and proof convergence strategies.

Responsibilities:

• Develop formal verification test plans to verify digital hardware designs.
• Work cross functionally with teams to analyze specifications and resolve bugs.
• Drive improvements to formal verification methodologies to enhance quality and efficiency.