Full-time
Field-Programmable Gate Arrays Engineer
Posted by ACL Digital • Hyderabad, Telangana, India
About the Role
RTL FPGA Design Engineers
Experience : 1-3 years
Location : Hyderabad
Expertise RTL Coding in Verilog, System Verilog or VHDL · Strong understanding of FPGA flow, Logic design, Digital design etc. · Knowledge in Xilinx FPGA architecture · Good Knowledge in Tcl, Python scripting.
Interested,please share your updated resume to
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