About the Role
Location: Bengaluru, India Experience: 10–15 years Industry: Semiconductors | AI | Networking | ASIC Design (Founding So C Team)
Role Overview
As the DFT Lead , you will be the primary architect and owner of the testability
strategy for our next-generation AI SOCs. This is a zero-to-one opportunity where you will
bridge the gap between initial architectural concepts and final production silicon. You will ensure
our high-performance AI/Networking chips meet the highest standards of test coverage, power
efficiency, and manufacturing yield in a fast-paced startup environment.
Key Responsibilities
● End-to-End Ownership: Define and drive the complete DFT strategy—from initial So C
specification through RTL, synthesis, and post-silicon validation.
● Architecture & Strategy: Architect comprehensive DFT solutions including Scan,
MBIST (Memory Built-In Self-Test), JTAG, Boundary Scan, and high-speed IO testing
tailored for AI workloads.
● Implementation E...
Role Overview
As the DFT Lead , you will be the primary architect and owner of the testability
strategy for our next-generation AI SOCs. This is a zero-to-one opportunity where you will
bridge the gap between initial architectural concepts and final production silicon. You will ensure
our high-performance AI/Networking chips meet the highest standards of test coverage, power
efficiency, and manufacturing yield in a fast-paced startup environment.
Key Responsibilities
● End-to-End Ownership: Define and drive the complete DFT strategy—from initial So C
specification through RTL, synthesis, and post-silicon validation.
● Architecture & Strategy: Architect comprehensive DFT solutions including Scan,
MBIST (Memory Built-In Self-Test), JTAG, Boundary Scan, and high-speed IO testing
tailored for AI workloads.
● Implementation E...
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