Full-time
DFT Engineer for Advance Process Node & Package Technology
Posted by MediaTek • Hsinchu City, Taiwan Province, Taiwan
About the Role
Job Description1. DFT architecture exploration & evaluation for next-gen process node & package technology of MediaTek:
* Scan chain insertion & ATPG pattern generation
* Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.)
* Diagnosis to help manufacture process improvement
2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC:
* PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation
* Develop & integrate DFT-related RTL design modules to test chip
#LI-ML2Requirement1. Expertise in Synopsys and/or Mentor DFT tools, and HDL simulators like Synopsys VCS
2. Fluency in script language including but not limited to TCL/Perl/Python
3. Experience about MBIST with state-of-the-art SRAM structure & EDA tools is big plus
4. Skill for RTL design & integration, and physical failure analysis(PFA) will also be plus
* Scan chain insertion & ATPG pattern generation
* Pattern validation through simulation & silicon analysis(pass/fail, shmoo, fail log, etc.)
* Diagnosis to help manufacture process improvement
2. Co-work with SoC architect, RTL designer, physical design engineer, and package engineer to define best architecture for 3D-IC:
* PPA(Performance/Power/Area) impact analysis & mitigation via DFT innovation
* Develop & integrate DFT-related RTL design modules to test chip
#LI-ML2Requirement1. Expertise in Synopsys and/or Mentor DFT tools, and HDL simulators like Synopsys VCS
2. Fluency in script language including but not limited to TCL/Perl/Python
3. Experience about MBIST with state-of-the-art SRAM structure & EDA tools is big plus
4. Skill for RTL design & integration, and physical failure analysis(PFA) will also be plus
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