Design Verification Engineer

Job title: Junior/Senior/Staff Design Verification Engineer

Location: KL/Penang (on-site)

Job Type: Full-time Malaysians only and/or have permit to work in Malaysia

We are growing and looking for self-motivated, multi-tasker, and demonstrated team-player. This position will be responsible for RTL verification, debug, functional coverage tasks, testplan development, and new verification methodology.

Key Responsibilities

-Develop and maintain UVM-based verification environments for IP designs.

-Create detailed test plans based on design specifications, architectural documents, and use-case scenarios.

-Implement constrained-random testbenches, scoreboards, and monitors to validate functional behavior.

-Perform coverage-driven verification, including:

o Functional coverage (covergroups, coverpoints)

o Code coverage (statement, branch, toggle)

o Assertion coverage (SystemVerilog assertions)

-Drive coverag...