Full-time

Design Verification Engineer

Posted by ACL Digital • Hyderabad, TELANGANA, India

📍 Hyderabad, TELANGANA 🕒 March 04, 2026

About the Role

Experience: 1-3 Years

Location: Hyderabad

Education: B.E./B.Tech. in ECE/EEE or M.E./M.Tech. in VLSI/Electronics


Roles and Responsibilities


  1. Strong expertise in UVM-based verification.
  2. Hands-on IP-level verification exposure and a solid understanding of serial protocols are a must.


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