About the Role
#ACL Digital is hiring: IP Verification Engineer – UVM Verification
We are looking for engineers with strong System Verilog UVM, behavioral modeling, and system-level performance verification experience.
Hands-on expertise in AXI4, No C protocols, and multi-master/multi-slave configurations is required.
Experience with DRAM memory controllers, traffic patterns, bandwidth & latency analysis is a plus.
Proficiency with VCS/Questa/Xcelium/Riviera and Vivado debug is essential.
Experience: 5–7 years
Notice Period: Immediate / 30 days
We are looking for engineers with strong System Verilog UVM, behavioral modeling, and system-level performance verification experience.
Hands-on expertise in AXI4, No C protocols, and multi-master/multi-slave configurations is required.
Experience with DRAM memory controllers, traffic patterns, bandwidth & latency analysis is a plus.
Proficiency with VCS/Questa/Xcelium/Riviera and Vivado debug is essential.
Experience: 5–7 years
Notice Period: Immediate / 30 days
Ready to Apply?
Submit your application today and take the next step in your career journey with ACL Digital.
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