Full-time

Design Verification Engineer

Posted by AdoreSys • Bayan Lepas, Penang, Malaysia

📍 Bayan Lepas, Penang 🕒 February 28, 2026

About the Role

  • Develop testbench components such as test, sequence libraries, bfm and monitor by using object oriented programming verification techniques following UVM methodology
  • Automate validation environment to improve activities such as test writing, regression running or coverage collection
  • Define detailed test plan from specification by working with architects and design engineers
  • Write and debug tests in UVM/C++
  • Incorporate function/code-coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tapeout

Qualifications:

  • Knowledge in C, Python, shell scripting
  • Great interpersonal and communication skills
  • Team player, critical thinker and problem solving skills

Fresh graduates and experienced candidates are welcome to apply

This role is open to Malaysia-based candidates only.

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