Full-time
Analog layout design engineer
Posted by Capgemini Engineering • Bengaluru, Karnataka, India
About the Role
Location: Bangalore
Your Role
To work independently on block/IP levels analog layout design from schematic.
Estimating the Area, Optimizing Floorplan, Routing and Verifications.
Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm Fin Fet and below.
Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts.
Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally.
Your Profile
Analog Layout Design (Block/IP level) - 4 to 10 Years
LVS/DRC Debugging
Fin FET Technology Node Experience (5nm, 7nm, 10nm, 14nm and below)
EDA Tools
Cadence Virtuoso Editor
Calibre RVE
Layout Optimization
Area estimation
Floorplanning
Routing
Your Role
To work independently on block/IP levels analog layout design from schematic.
Estimating the Area, Optimizing Floorplan, Routing and Verifications.
Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm Fin Fet and below.
Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts.
Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally.
Your Profile
Analog Layout Design (Block/IP level) - 4 to 10 Years
LVS/DRC Debugging
Fin FET Technology Node Experience (5nm, 7nm, 10nm, 14nm and below)
EDA Tools
Cadence Virtuoso Editor
Calibre RVE
Layout Optimization
Area estimation
Floorplanning
Routing
Ready to Apply?
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