About the Role
A well-funded AI and semiconductor startup is seeking a Junior/Intermediate Design Verification Engineer in Toronto, offering a competitive salary of CA$150K to CA$200K plus equity. Responsibilities include writing SystemVerilog/UVM testbenches, defining verification plans, and automating test execution. Ideal candidates should have 1-5 years of experience, familiarity with verification methodologies, and strong scripting skills. The role offers mentorship from senior engineers and the chance to work in a dynamic hybrid environment.
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